Archives
ClearSpeed User Group 07 Presentations
The CSUG 07 abstracts with links to available presentations are listed below:
ClearSpeed User Group: Welcome and Overview (PDF)
Host: Simon McIntosh-Smith, VP Customer Applications
Abstract: Welcome, overview and announcements.
Introduction to Accelerating Applications (PDF)
Speaker: Kristopher Buschelman, Engineering Manager: CSXL at ClearSpeed Technology
Abstract: The ClearSpeed Advance family of boards offers exciting possibilities for accelerating applications by providing up to 80.4 GF/s of compute performance. But not all applications are good candidates for this acceleration. In this talk, we will analyze when an application will benefit from acceleration.
CSX600 – Applications and results (PDF)
Speaker: Jamil Appa, Senior Principle Engineer, BAE Systems
Abstract: Results and lessons learned from accelerating HPC applications with solver algorithms and parallel search
Ab-Initio Electronic Structure Theory on ClearSpeed (PDF)
Speaker: Phil Brown, PhD student at Bristol University
Abstract: Electronic structure theory enables the accurate calculation of molecular interactions, but is computationally expensive. Density functional theory offers a good balance of speed and accuracy. Its bottlenecks are calculating the Coulomb interactions (classical eletrostatic) and exchange-correlation energy (quantum effects). The treatment of exchange-correlation uses quadrature, which transfers easily to the ClearSpeed architecture: the algorithm can be finely parallelized by dividing the quadrature grid into small batches. We reformulate the algorithm for the Coulomb problem to move work into quadrature, which we again pass to ClearSpeed boards. We generate and store very large matrices on the boards, leaving a DGEMM as our bottleneck. Using the X620, this can be performed at 50GFlops per board.
Identify Bottlenecks and Speed Up Your Code Using ClearSpeed Development Tools (PDF)
Speaker: Thierry Schuepbach, Swiss Institute of Bioinformatics
Abstract: Programming ClearSpeed CSX600 has become straightforward thanks to the C like compiler. However, the generated code does not always deliver the maximum performance the CSX600 processor is capable of.
We shall present a test study in three steps on the computation of non-bonded interactions which is by far the most consuming algorithm found in standard molecular dynamics. First, different approaches in the deployment of the algorithm will be considered and benchmarked. Second, ClearSpeed Visual Profiler will be used to identify bottlenecks. Finally, we will show how one can, to some extent, modify the Cn code to overcome the problems or, if not possible, migrate to assembly inlined code.
The ClearSpeed Software Tool Chain (PDF)
Speaker: Matthew Fyles, Software Debug/Profiler Team Lead at ClearSpeed
Abstract: An overview of the features of the ClearSpeed software tool chain, including features available in release 3 that is now in beta. Demonstration showing everything discussed in the presentation running live as it sits on top of the command line tools.
Using ClearSpeed Accelerators in Parallel from Very High-Level Languages (PDF)
Speaker: Steve Reinhardt, VP of Joint Research at Interactive Supercomputing
Abstract: ClearSpeed chips offer astonishing acceleration for key algorithms in diverse industries. So far, their use has been most prevalent for users willing to remap their existing C/C++/Fortran applications. A wider audience is possible by addressing applications written in very high-level productivity languages such as Python, MATLAB(R) and R. Star-P enables straightforward parallel execution of VHLL programs. This talk will cover recent experiments linking ClearSpeed library routines into the Star-P infrastructure for parallel acceleration, and the future of such linkages.
Acceleration of a 3D Flow Solver (PDF)
Speaker: Tobias Brandvik, PhD student at Whittle Laboratory, Cambridge University
Abstract: The calculation of the fluid flow around a given geometry is a common operation in the turbomachinery design process. These simulations are time-consuming and can take weeks to complete even on large clusters.
In an attempt to reduce the run time, a simplified version of an existing flow solver written in Fortran has been ported to the ClearSpeed Advance board. The algorithm used in the solver lends itself well to SIMD parallelisation, but care must be taken to get the most out of the ClearSpeed architecture. Several lessons learnt during the porting process are presented here, ranging from high-level design decisions to low-level coding tips and tricks.
The ClearSpeed Visual Profiler (PDF)
Speaker: Matthew Fyles, ClearSpeed
Abstract: A concise exploration of the performance tuning capability of the ClearSpeed Visual Profiler. Features and their profiling capabilities will be discussed, including those available in release 3 (beta), followed by a profiling demonstration using real application code.