Training
Here are online, self-paced technical courses related to develping accelerated applications:
ClearSpeed Developer Training Course
Introduction to ClearSpeed Acceleration (PDF)
Introduces reader to ClearSpeed and provides training course foundation.
Overview of Architecture (PDF)
Includes acceleration examples and porting considerations.
ClearSpeed Programming Model: Introduction (PDF)
Intended to help developers get started with the ClearSpeed toolchain; includes an example of taking a basic serial program towards a parallel implementation.
ClearSpeed Programming Model: Card Side Libraries (PDF)
Covers code scalability, general utilities, performance enhancement, Fourier transformations and pseudo-random number generators.
ClearSpeed Programming Model: Optimizing Performance (PDF)
Efficient computation, memory optimization, profiling, latency hiding and compiler optimization levels are reviewed.
ClearSpeed Programming Model: Case Studies (PDF)
A problem is presented with an initial implementation in Cn and then improved through a series of iterative improvements.
ClearSpeed Software Training
ClearSpeed Software Development Environment: Advanced (PDF)
A thorough examination of the ClearSpeed Development Environment including hardware and software installation, hardware and SDK overviews, performance considerations and application samples.
ClearSpeed User Group 08 Presentations
Abstracts of presentations given at the recent CSUG and ISC’08 with links to available presentations are listed below:
ClearSpeed User Group: Welcome, Roadmap and New Products (PDF)Speaker: Simon McIntosh-Smith, VP of Customer Applications at ClearSpeed Technology
Abstract: Simon McIntosh-Smith will be disclosing an exciting raft of new hardware and software products from ClearSpeed, not officially announced until later in the week.
Speakers: Dr Richard Sessions, Senior Research Fellow at the Department of Biochemistry
University of Bristol and Simon McIntosh-Smith, ClearSpeed
Abstract: This presentation, given at the ISC’08 Pre-Conference Scientific Session, describes how next generation, cutting edge drug docking codes can be ported to HPC accelerators and achieve orders of magnitude more performance, while maintaining the required high accuracy and high reliability. Real science is already being performed using the accelerated code.
Speaker: Simon McIntosh-Smith, VP of Customer Applications at ClearSpeed Technology
Abstract: This presentation, given at ISC08, introduces ClearSpeed’s new, CSX700-based many-core HPC accelerators, with class-leading 64-bit performance, performance per watt, and reliability and accuracy features. The presentation explores how hybrid Petascale systems can be built from such multi-core accelerators, with orders of magnitude reductions in cost, size and power consumption while maintaining the high reliability, accuracy and ease of use demanded by Petascale applications.
ClearSpeed Acceleration Applied to Passive Coherent Location (PDF)
Speaker: Dr Khomotso Kganyago, Technical and Operations Manager at the Centre for High Performance Computing in Capetown, South Africa
Abstract: This case study examines performance and accuracy results for an aircraft tracking algorithm running on a non-assisted host and a ClearSpeed accelerated host. Performance gains are seen on the ClearSpeed accelerated host when the problem is either data parallel with high computation to data transfer ratio, or if linear algebra problems of a specific size are being solved. In order to be candidates for parallelization, applications need to be data parallel, have a high computation to data movement ratio and small working data sets. An application is also a good candidate for of acceleration if a high percentage of application execution time is taken up by any linear algebra routines supported by ClearSpeed's CSXL library.
The ClearSpeed programming model has a less than two week learning curve, as it is fairly straight forward. Users experienced in parallel programming will find ClearSpeed programming even easier to adjust to.
Experiences in a ClearSpeed Multi-card Environment (PDF)
Speaker: Dr Thomas Steinke, HPC research & consulting at Konrad-Zuse-Zentrum für Informationstechnik Berlin (ZIB)
Abstract: This talk examines benefits found by using hardware accelerators including better hardware utilization, extending applications areas and better performance per watt per floor space.
IMSL Numerical Libraries Accelerated with the ClearSpeed Advance Accelerators (PDF)
More information: Using the IMSL C Numerical Library with ClearSpeed Technology
Speaker: Tim Leite, Director of Corporate Development and Education Programs at Visual Numerics, Inc.
Abstract: The IMSL C Numerical Library contains a comprehensive set of mathematical and statistical algorithms used in a variety of application domains. Compatibility testing has been completed between the IMSL C Library and the ClearSpeed Advance Accelerators. This presentation will cover some of the aspects of the compatibility such as linking the IMSL Library with the ClearSpeed high performance technology, benchmark results, and application areas of interest. In addition a brief overview of the IMSL C Numerical Library covering the computational areas of support will also be provided.
Productivity Solution for ClearSpeed Accelerators (PDF)
Speaker: Dave Gibson, VP of Sales at Interactive Supercomputing
Abstract: Interactive Supercomputing and ClearSpeed have joined forces to deliver accelerator technology to the engineering, scientific and analytical community - today. The industry is hyping accelerator technology that requires a significant development effort to really take advantage of these technologies and requires technical expertise that has yet to be established with domain experts. With Star-P and ClearSpeed accelerators, domain experts can improve the execution time on existing or new algorithms, models and/or simulations without having to spent the development time normally required and do not have to acquire the technical expertise. This talk will illustrate the use modes of Star-P with ClearSpeed accelerators and provide an outline of how the technical community can expand the level of support of ClearSpeed accelerators with the Star-P parallel programming platform.
SGI Accelerator Enabling Program (PDF)
Speaker: Bill Brown, Server Product Marketing Manager at SGI
Abstract: SGI is expanding its commitment to the accelerator technology market by driving the Accelerator Enabling Program (AEP), an initiative with the goal of working with ISVs and key customers to provide the best accelerator choice for different scientific domains. The AEP delivers increased focus on the best accelerator choice on how and when to use accelerators on SGI server platforms. Through the AEP, ISVs and customers will have access to dozens of accelerator technology experts from SGI and participating partners. By collaborating with these experts, developers and customers can optimize their codes to run on the accelerator that best suits the needs of their applications. Customer benefit is pre-approved partners - SGI’s engineering team has evaluated their capabilities and stand behind them as a supplier.
The Method of Moments: The Perfect ClearSpeed Application (PDF)
Speaker: Tim Lanfear, Technical Consultant at ClearSpeed Technology
Abstract: For many years the Method of Moments has been used for solving Maxwell's equations so as to calculate the interaction between electromagnetic waves and a target. The time consuming part of the algorithm is the solution of a large set of linear equations with complex coefficients. Linear algebra operations on dense matrices are an excellent fit to ClearSpeed accelerators and the potential benefits of applying acceleration technology to this computational electromagnetics method are described.